`timescale  1 ns/1 ps

module top_tb (); 
reg                     clk = 0;
always
    #(1s/100_000_000/2) clk = ~clk;

reg                     rst = 1;
initial
begin
    #1us; rst = 0;
    #1us; rst = 1;
end

top topEx01
(
    .clk             (  clk                 ),
    .rst             (  rst                 ),
    .sys_clock_pulse (  sys_clock_pulse     )
);
endmodule
